[PATCH v5 01/26] ARM: OMAP2+: gpmc: Add platform data
Add a platform data structure for GPMC. It contains all the necessary platform information that needs to be passed from platform init code to GPMC dri
View Article[PATCH v5 02/26] ARM: OMAP2+: gpmc: Add gpmc timings and settings to platform...
Add device_timings, gpmc_timings and gpmc_setting to gpmc platform data. Signed-off-by: Roger Quadros <rogerq@ti.com> --- include/linux/omap-gpmc.h
View Article[PATCH v5 03/26] memory: omap-gpmc: Introduce GPMC to NAND interface
The OMAP GPMC module has certain registers dedicated for NAND access and some NAND bits mixed with other GPMC functionality. For the NAND dedicated r
View Article[PATCH v5 04/26] mtd: nand: omap2: Use gpmc_omap_get_nand_ops() to get NAND...
Deprecate nand register passing via platform data and use gpmc_omap_get_nand_ops() instead. Signed-off-by: Roger Quadros <rogerq@ti.com> --- arch/ar
View Article[PATCH v5 05/26] memory: omap-gpmc: Add GPMC-NAND ops to get writebufferempty...
This is needed by OMAP NAND driver to poll the empty status of the writebuffer. Signed-off-by: Roger Quadros <rogerq@ti.com> --- drivers/memory/omap
View Article[PATCH v5 06/26] mtd: nand: omap2: Switch to using GPMC-NAND ops for...
Instead of accessing the gpmc_status register directly start using the gpmc_nand_ops->nand_writebuffer_empty() helper to check write buffer empty stat
View Article[PATCH v5 07/26] memory: omap-gpmc: Implement IRQ domain for NAND IRQs
GPMC provides 2 interrupts for NAND use. i.e. fifoevent and termcount. Use IRQ domain for this. NAND device tree node can then get the necessary inter
View Article[PATCH v5 08/26] mtd: nand: omap: Copy platform data parameters to...
Copy all the platform data parameters to the driver's local data structure 'omap_nand_info' and use it in the entire driver. This will make it easer f
View Article[PATCH v5 09/26] mtd: nand: omap: Clean up device tree support
Move NAND specific device tree parsing to NAND driver. The NAND controller node must have a compatible id, register space resource and interrupt reso
View Article[PATCH v5 10/26] mtd: nand: omap: Update DT binding documentation
Add compatible id and interrupts. The NAND interrupts are provided by the GPMC controller node. Signed-off-by: Roger Quadros <rogerq@ti.com> --- Doc
View Article[PATCH v5 11/26] memory: omap-gpmc: Prevent mapping into 1st 16MB
We have been preventing mapping GPMC children in the first 1MB but really it has to be the first 16MB as the minimum GPMC partition size is 16MB. Als
View Article[PATCH v5 12/26] memory: omap-gpmc: Move device tree binding to correct location
omap-gpmc.c is a memory controller so move the binding to the right place. Signed-off-by: Roger Quadros <rogerq@ti.com> --- Documentation/devicetree
View Article[PATCH v5 13/26] memory: omap-gpmc: Support general purpose input for WAITPINs
OMAPs can have 2 to 4 WAITPINs that can be used as general purpose input if not used for memory wait state insertion. The first user will be the OMAP
View Article[PATCH v5 14/26] memory: omap-gpmc: Reserve WAITPIN if needed for WAIT...
If the device attached to GPMC wants to use the WAIT pin for WAIT monitoring then we reserve it internally for exclusive use. Signed-off-by: Roger Qu
View Article[PATCH v5 15/26] memory: omap-gpmc: Support WAIT pin edge interrupts
OMAPs can have 2 to 4 WAITPINs that can be used as edge triggered interrupts if not used for memory wait state insertion. Support these interrupts vi
View Article[PATCH v5 16/26] memory: omap-gpmc: Prevent GPMC_STATUS from being accessed...
GPMC_STATUS register is private to the GPMC module and must not be accessed directly by NAND driver through the gpmc_regs. They must use gpmc_omap_ge
View Article[PATCH v5 17/26] mtd: nand: omap2: Implement NAND ready using gpiolib
The GPMC WAIT pin status are now available over gpiolib. Update the omap_dev_ready() function to use gpio instead of directly accessing GPMC register
View Article[PATCH v5 18/26] ARM: dts: dra7: Fix NAND device nodes.
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC driver now implements gpiochip and irqchip so ena
View Article[PATCH v5 19/26] ARM: dts: dra7x-evm: Provide NAND ready pin
On these boards NAND ready pin status is avilable over GPMC_WAIT0 pin. Read speed increases from 13768 KiB/ to 17246 KiB/s. Write speed was unchanged
View Article[PATCH v5 20/26] ARM: dts: am437x: Fix NAND device nodes
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC driver now implements gpiochip and irqchip so ena
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