drm/vc4: Modesetting fixes
This series fixes the highest priority problems reported from the driver getting enabled in Raspbian: modesetting on HDMI was broken if you weren't at
View Article[PATCH 1/6] drm/vc4: Fix a framebuffer reference leak on async flip interrupt.
We'd need X to queue up an async pageflip while another is outstanding, and then take a SIGIO. I think X actually avoids sending out the next pagefli
View Article[PATCH 2/6] drm/vc4: Bring HDMI up from power off if necessary.
If the firmware hadn't brought up HDMI for us, we need to do its power-on reset sequence (reset HD and and clear its STANDBY bits, reset HDMI, and lea
View Article[PATCH 3/6] drm/vc4: Add another reg to HDMI debug dumping.
This is also involved in the HDMI setup sequence so it's nice to see it. Signed-off-by: Eric Anholt <eric@anholt.net> --- This patch and the next on
View Article[PATCH 4/6] drm/vc4: Fix the name of the VSYNCD_EVEN register.
It's used for delaying vsync in interlaced mode. Signed-off-by: Eric Anholt <eric@anholt.net> --- drivers/gpu/drm/vc4/vc4_crtc.c | 2 +- drivers/gpu
View Article[PATCH 5/6] drm/vc4: Fix setting of vertical timings in the CRTC.
It looks like when I went to add the interlaced bits, I just took the existing PV_VERT* block and indented it, instead of copy and pasting it first.
View Article[PATCH 6/6] drm/vc4: Initialize scaler DISPBKGND on modeset.
We weren't updating the interlaced bit, so we'd scan out incorrectly if the firmware had brought up the TV encoder and we were switching to HDMI. Sig
View Article[PATCH] ASoC: cht_bsw_rt5645: Enable jack detection
From: Carlo Caione <carlo@endlessm.com> Add missing DAPM pins and enable jack detection on those pins for Cherrytrail and Braswell. Signed-off-by: C
View Article[PATCH] ARM: vdso: Mark vDSO code as read-only
Although the arm vDSO is cleanly separated by code/data with the code being read-only in userspace mappings, the code page is still writable from the
View Article[PATCH 0/4] Updates to EDAC and AMD MCE driver
This patchset mainly provides necessary EDAC bits to decode errors occuring on Scalable MCA enabled processors and also updates AMD MCE driver to get
View Article[PATCH 1/4] EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors
For Scalable MCA enabled processors, errors are listed per IP block. And since it is not required for an IP to map to a particular bank, we need to us
View Article[PATCH 2/4] x86/mce/AMD: Fix logic to obtain block address
In upcoming processors, the BLKPTR field is no longer used to indicate the MSR number of the additional register. Insted, it simply indicates the pres
View Article[PATCH 3/4] x86/mce: Clarify comments regarding deferred error
The Deferred field indicates if we have a Deferred error. Deferred errors indicate errors that hardware could not fix. But it still does not cause any
View Article[PATCH 4/4] x86/mce/AMD: Add comments for easier understanding
In an attempt to help folks not very familiar with the code to understand what the code is doing, adding a bit of helper comments around some more imp
View Article[PATCH] lkdtm: add test for executing .rodata
Make sure that the read-only data section isn't executable. Signed-off-by: Kees Cook <keescook@chromium.org> --- drivers/misc/lkdtm.c | 28 +++++++++
View Article[PATCH v2] dmaengine: pxa_dma: fix cyclic transfers
While testing audio with pxa2xx-ac97, underrun were happening while the user application was correctly feeding the music. Debug proved that the cyclic
View Article[PATCH RESEND v3 0/3] PCI: hv: New paravirtual PCI front-end driver
From: Jake Oshins <jakeo@microsoft.com> This version incorporates more feedback from Bjorn Helgaas. Most notably, I removed some debugging code and
View Article[PATCH RESEND v3 1/3] PCI: Add fwnode_handle to pci_sysdata
From: Jake Oshins <jakeo@microsoft.com> This patch adds an fwnode_handle to struct pci_sysdata, which is used by the next patch in the series when tr
View Article[PATCH RESEND v3 2/3] PCI: irqdomain: Look up IRQ domain by fwnode_handle
From: Jake Oshins <jakeo@microsoft.com> This patch adds a second way of finding an IRQ domain associated with a root PCI bus. After looking to see i
View Article[PATCH RESEND v3 3/3] PCI: hv: New paravirtual PCI front-end for Hyper-V VMs
From: Jake Oshins <jakeo@microsoft.com> This patch introduces a new driver which exposes a root PCI bus whenever a PCI Express device is passed throu
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