[PATCH 08/21] coresight: etm3x: unlocking tracers in default arch init
Calling function 'smp_call_function_single()' to unlock a tracer and calling it again right after to perform the default initialisation doesn't make s
View Article[PATCH 09/21] coresight: etm3x: splitting struct etm_drvdata
Splitting "etm_drvdata" in two sections, one for the HW specific data and another for user configuration. That way it is easier to manipulate and zer
View Article[PATCH 10/21] coresight: etm3x: adding operation mode for etm_enable()
Adding a new mode to source API enable() in order to distinguish where the request comes from. That way it is possible to perform different operation
View Article[PATCH 11/21] coresight: etm3x: set progbit to stop trace collection
There is no need to use the event enable's "always false" event to stop trace collection. For that purpose setting the programming bit (ETMCR:10) is
View Article[PATCH 12/21] coresight: etm3x: changing default trace configuration
Changing default configuration to include the entire address range rather than just the kernel. That way traces are more inclusive and it is easier t
View Article[PATCH 13/21] coresight: etm3x: consolidating initial config
There is really no point in having two functions to take care of doing the initial tracer configuration. As such moving everything to 'etm_set_defaul
View Article[PATCH 14/21] coresight: etm3x: implementing user/kernel mode tracing
Adding new mode to limit tracing to kernel or user space. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- drivers/hwtracing/coresigh
View Article[PATCH 15/21] coresight: etm3x: implementing perf_enable/disable() API
That way traces can be enabled and disabled automatically from the Perf subystem using the PMU abstraction. Signed-off-by: Mathieu Poirier <mathieu.p
View Article[PATCH 16/21] coresight: etb10: moving to local atomic operations
Moving to use local atomic operations to take advantage of the lockless implementation, something that will come handy when the ETB is accessed from t
View Article[PATCH 17/21] coresight: etb10: adding operation mode for sink->enable()
Adding an operation mode to the sink->enable() API in order to prevent simultaneous access from different callers. TPIU and TMC won't be supplemented
View Article[PATCH 18/21] coresight: etb10: implementing AUX API
Adding an ETB10 specific AUX area operations to be used by the perf framework when events are initialised. Part of this operation involves modeling t
View Article[PATCH 19/21] coresight: etm-perf: new PMU driver for ETM tracers
Perf is a well known and used tool for performance monitoring and much more. A such it is an ideal candidate for integration with coresight based HW t
View Article[PATCH 20/21] coresight: introducing a global trace ID function
TraceID values have to be unique for all tracers and consistent between drivers and user space. As such introducing a central function to be used whe
View Article[PATCH 21/21] drivers/hwtracing: make coresight-* explicitly non-modular
From: Paul Gortmaker <paul.gortmaker@windriver.com> None of the Kconfig currently controlling compilation of any of the files here are tristate, mean
View Article[PATCH v2 1/7] QE: Add IC, SI and SIRAM document to device tree bindings.
Add IC, SI and SIRAM document of QE to Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> ---
View Article[PATCH v2 2/7] QE: Add ucc hdlc document to bindings
Add ucc hdlc document to Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> --- Changes
View Article[PATCH v2 3/7] QE: Add uqe_serial document to bindings
Add uqe_serial document to Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> --- Cha
View Article[PATCH v2 4/7] bindings: move cpm_qe binding from powerpc/fsl to soc/fsl
cpm_qe is supported on both powerpc and arm. and the QE code has been moved from arch/powerpc into drivers/soc/fsl, so move cpm_qe binding from powerp
View Article[PATCH v2 5/7] T104xD4RDB: Add qe node to t104xd4rdb
add qe node to t104xd4rdb.dtsi and t1040si-post.dtsi. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> --- Changes for v2 - rebase arch/power
View Article[PATCH v2 6/7] T104xRDB: Add qe node to t104xrdb
add qe node to t104xrdb.dtsi Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> --- Changes for v2 - rebase arch/powerpc/boot/dts/fsl/t104xrdb.
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